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Extensible architecture for digital signal processing
Extensible architecture for digital signal processing
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机译：用于数字信号处理的可扩展架构
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摘要
An architecture for implementing a plurality of digital signal processors defined by a plurality of physically distinct processing modules connected by a plurality of high speed digital interconnects is described. Wherein the first plurality of first modules have a plurality of analog signal inputs or a plurality of digital signal inputs, perform a first set of a plurality of digital processing functions, and a first plurality of digital interconnects Arranged to produce output. A second plurality of second modules receives the first plurality of digital interconnect outputs, performs a second set of digital processing functions, and outputs a second plurality of digital interconnect outputs. Arranged to generate. A third plurality of third modules receive these second plurality of digital interconnect outputs and perform a third set of digital processing functions to provide a plurality of analog signal outputs or a plurality of digital signals. Arranged to produce output. The architecture includes a plurality of first modules such that the signal processing required for the digital signal processor is achieved by distributing the processing over a combination of the number of selected first, second, and third modules. Expansion is possible by selecting the number of modules, the number of second modules, and the number of third modules and the interconnections between them.
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