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PER THREAD CACHE-LINE ALLOCATION MECHANISM IN SHARED PARTITIONED CACHES IN MULTI-THREADED PROCESSORS
PER THREAD CACHE-LINE ALLOCATION MECHANISM IN SHARED PARTITIONED CACHES IN MULTI-THREADED PROCESSORS
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机译：多线程处理器中共享分区缓存中的每个线程缓存行分配机制
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摘要
PROBLEM TO BE SOLVED: To provide systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor.SOLUTION: In a processing system, a memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated to the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions (main/auxiliary). The cache entry is allocated to one of the portions of the cache on the basis of the configuration register and the partitioning register.SELECTED DRAWING: Figure 4
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