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DEBUGGING METHOD SPECIFICALLY FOR FPGA OF HIGH-END FAULT-TOLERANT COMPUTER BASED ON SOFTWARE-HARDWARE ARCHITECTURE, AND DEVICE THEREOF
DEBUGGING METHOD SPECIFICALLY FOR FPGA OF HIGH-END FAULT-TOLERANT COMPUTER BASED ON SOFTWARE-HARDWARE ARCHITECTURE, AND DEVICE THEREOF
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机译：基于软件-硬件架构的高端容错计算机专用的debugging方法及其装置
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摘要
The present invention relates to the field of high-end computer design, and provides a debugging method specifically for an FPGA of a high-end fault-tolerant computer based on a software-hardware architecture, and a device thereof. Debugging information needed is obtained using the software platform of a superordinate computer to control the FPGA debugging logic, the logic functions being configurable and the captured information being dynamically displayed in the software. The debugging logic of the FPGA organizes, according to the configuration done by the software of the superordinate computer, the signal that needs to be captured into a specific format, and stores same into the RAM of the FPGA; the interface part of the debugging logic encapsulates the data into data packets defined by a communications protocol, and transmits same to a USB interface. The software of the superordinate computer receives the data packets transmitted by the debugging logic, decapsulates the data packets, stores same into a MySQL database, and simultaneously displays same dynamically on the software interface. The software-hardware communications are in accordance to the dedicated communications protocol. The analysis result is better than the result of logic analyzers, and substantial capital is conserved. The maintenance of the debugging system is more economic and easier, thereby substantially enhancing the usability of the system and reducing debugging risks.
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