首页> 外国专利> DEVICE FOR MULTIPLICATION OF ARBITRARY MODULO 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c02e00140011200000026060f001a00ffffffff000010000000c0ffffffa1ffffff00010000810100000b00000026060f000c004d61746854797065000050001c000000fb0220ff00000000000090010000000004020020417269616c000000a40f0a0c70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01000008000000320a8801d5000100000069791c000000fb02e0fe00000000000090010000000004020020417269616c000000e1040a7e70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01010004000000f001000008000000320a400133000100000061790a00000026060f000a00ffffffff0100000000001c000000fb021000070000000000bc02000000cc0102022253797374656d0048e50c664800000a0021008a01000000000000000088f21200040000002d01000004000000f0010100030000000000AND 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c

DEVICE FOR MULTIPLICATION OF ARBITRARY MODULO 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c02e00140011200000026060f001a00ffffffff000010000000c0ffffffa1ffffff00010000810100000b00000026060f000c004d61746854797065000050001c000000fb0220ff00000000000090010000000004020020417269616c000000a40f0a0c70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01000008000000320a8801d5000100000069791c000000fb02e0fe00000000000090010000000004020020417269616c000000e1040a7e70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01010004000000f001000008000000320a400133000100000061790a00000026060f000a00ffffffff0100000000001c000000fb021000070000000000bc02000000cc0102022253797374656d0048e50c664800000a0021008a01000000000000000088f21200040000002d01000004000000f0010100030000000000AND 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c

机译：DEVICE期任意乘法MODULO 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c02e00140011200000026060f001a00ffffffff000010000000c0ffffffa1ffffff00010000810100000b00000026060f000c004d61746854797065000050001c000000fb0220ff00000000000090010000000004020020417269616c000000a40f0a0c70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01000008000000320a8801d5000100000069791c000000fb02e0fe00000000000090010000000004020020417269616c000000e1040a7e70f01200e8b1f377f1b1f3772040f577e50c6648040000002d01010004000000f001000008000000320a400133000100000061790a00000026060f000a00ffffffff0100000000001c000000fb021000070000000000bc02000000cc0102022253797374656d0048e50c664800000a0021008a01000000000000000088f21200040000002d01000004000000f0010100030000000000AND 010009000003c900000002001c00000000000500000009020000000005000000020101000000050000000102ffffff00050000002e0118000000050000000b0200000000050000000c

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摘要

The invention relates to computer engineering and automatics and is intended for multiplication of arbitrary modulo EMBED Equation.3 and EMBED Equation.3 residues of residue number system. A device for multiplication of arbitrary modulo EMBED Equation.3 and EMBED Equation.3 residues comprises first and second input registers, output register, first and second decode circuits, first and second groups of OR gates, each group containing EMBED Equation.3 OR gates, first and second groups of AND gates, each group containing EMBED Equation.3 AND gates, switch, modulo two adder, first, second, third and fourth OR gates. The device further comprises an encoder, thirds, fourth and fifth groups of AND gates, group of key elements, modulo EMBED Equation.3 adder, modulo EMBED Equation.3 adder, third and fourth group of OR gates. The technical result is in device enhancement due to execution of multiplication operator not only in positive number domain but in negative one.

机译：本发明涉及计算机工程和自动化领域，并且用于残差数系统的任意模EMBED方程式3和EMBED方程式3的残差的乘法。一种用于将任意模EMBED公式3和EMBED公式3残差相乘的设备，包括第一和第二输入寄存器，输出寄存器，第一和第二解码电路，第一和第二组或门，每组包含EMBED公式3或门，第一和第二组“与”门，每组包含EMBED Equation.3“与”门，开关，模2加法器，第一，第二，第三和第四“或”门。该设备进一步包括编码器，第三，第四和第五组与门，一组关键元件，模EMBED Equation.3加法器，模EMBED Equation.3加法器，第三和第四组或门。技术结果是由于不仅在正数域而且在负数域执行乘法运算符，从而提高了设备性能。

著录项

公开/公告号UA110913C2

专利类型
公开/公告日2016-02-25

原文格式PDF
申请/专利权人 HORBENKO IVAN DMYTROVYCH;KRASNOBAIEV VIKTOR ANATOLIIOVYCH;KURCHANOV VALERII MYKYTOVYCH;YANKO ALINA SERHIIVNA;KOSHMAN SERHII OLEKSANDROVYCH;HORBENKO YURII IVANOVYCH;
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申请/专利号UA20150005097
发明设计人 HORBENKO IVAN DMYTROVYCH;KRASNOBAIEV VIKTOR ANATOLIIOVYCH;KURCHANOV VALERII MYKYTOVYCH;YANKO ALINA SERHIIVNA;KOSHMAN SERHII OLEKSANDROVYCH;HORBENKO YURII IVANOVYCH;
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申请日2015-05-25
分类号G06F7/52;G06F7/523;
国家 UA
入库时间 2022-08-21 14:23:08

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