Method for controlling an internal supply voltage based on a clock frequency of an external clock signal and a look-up table

• 1. 用于在存储器装置中提供不同时钟频率的内部时钟信号的设备和方法 [P] . 中国专利： CN110199353A . 2019-09-03
• 2. 用来降低内部时钟信号的时钟频率的集成电路和方法 [P] . 中国专利： CN1157671C . 2004.07.14
• 3. METHOD FOR CONTROLLING AN INTERNAL SUPPLY VOLTAGE BASED ON A CLOCK FREQUENCY OF AN EXTERNAL CLOCK SIGNAL AND A LOOK-UP TABLE [P] . 美国专利： US2016141007A1 . 2016-05-19

  机译： 基于外部时钟信号的时钟频率和查找表的内部电源电压控制方法

• 4. Semiconductor memory device for controlling an internal supply voltage based on a clock frequency of an external clock signal and a look-up table [P] . 美国专利： US9269406B2 . 2016-02-23

  机译： 用于基于外部时钟信号的时钟频率和查找表来控制内部电源电压的半导体存储装置

• 5. Methods of generating internal clock signals from external clock signals and of measuring the frequency of external clock signals and related frequency measuring circuits and semiconductor memory devices [P] . 美国专利： US7274185B2 . 2007-09-25

  机译： 从外部时钟信号产生内部时钟信号以及测量外部时钟信号的频率的方法以及相关的频率测量电路和半导体存储器件

• 1. A SCHEDULING SCHEME WITH DYNAMIC FREQUENCY CLOCKING AND MULTIPLE VOLTAGES FOR LOW POWER DESIGNS [J] . Wen Dongxin, Wang Ling, Yang Xiaozong 电子科学学刊（英文版） . 2007,第004期
• 2. Numerical Prediction Methods for Clock Deviation Based on Two-Way Satellite Time and Frequency Transfer Data [J] . GUO Hairong, YANG Yuanxi, HE Haibo 地球空间信息科学学报：英文版 . 2008,第002期
• 3. Multi-objective optimization for voltage and frequency control of smart grids based on controllable loads [J] . Yaxin Wang, Donglian Qi, Jianliang Zhang 全球能源互联网：英文版 . 2021,第002期
• 4. Adaptive controller design based on input-output signal selection for voltage source converter high voltage direct current systems to improve power system stability [J] . Abdolkhalegh Hamidi, Jamal Beiza, Ebrahim Babaei, 中南大学学报（英文版） . 2016,第009期
• 5. An autonomous low-power architecture for a chip multi-processor - adaptive-universal control of clock frequency, supply voltage and body bias [J] . Masayuki Miyazaki, Goichi Ono, Hidetoshi Tanaka, 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2003,第89期
• 6. An autonomous low-power architecture for a chip multi-processor - adaptive-universal control of clock frequency, supply voltage and body bias [J] . Masayuki Miyazaki, Goichi Ono, Hidetoshi Tanaka, 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2003,第89期
• 7. Formal Online Methods for Voltage/Frequency Control in Multiple Clock Domain Microprocessors [J] . Qiang Wu, Philo Juang, Margaret Martonosi, Computer architecture news . 2004,第5期
• 8. Formal online methods for voltage/frequency control in multiple clock domain microprocessors [C] . Qiang Wu, Philo Juang, Margaret Martonosi, International conference on Architectural support for programming languages and operating systems . 2004
• 9. Low Voltage Clocking Methodologies for Nanoscale ICs [D] . Liu, Weicheng. 2018
• 10. A coupled SYSTEM of intracellular Ca2+ clocks and surface membrane voltage clocks controls the timekeeping mechanism of the heart’s pacemaker [O] . Edward G. Lakatta, Victor A. Maltsev, Tatiana M. Vinogradova -1
• 11. Formal Online Methods for Voltage/Frequency Control in Multiple Clock Domain Microprocessors [O] . Qiang Wu, Philo Juang, Margaret Martonosi, 2004

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