NOVEL METHOD OF DESIGN RULE CHECK FOR OFF-GRID IRREGULAR LAYOUT WITH ON-GRID DESIGN RULE CHECK DECK

• 1. 布局图设计规则检查的方法与计算机可读取记录介质 [P] . 中国专利： CN101206679B . 2010.09.15
• 2. 布局图设计规则检查的方法与计算机可读取记录介质 [P] . 中国专利： CN101206679A . 2008-06-25
• 3. Method of design rule check for off-grid irregular layout with on-grid design rule check deck [P] . 美国专利： US9798851B2 . 2017-10-24

  机译： 带有并网设计规则检查平台的离网不规则布局设计规则检查方法

• 4. CHECK TOOL AND CHECK METHOD FOR DESIGN RULE CHECK RULE DECK OF INTEGRATED CIRCUIT LAYOUT [P] . US2021383053A1 . 2021-12-09

  机译： 检查工具和检查集成电路布局的设计规则检查规则甲板的工具和检查方法

• 5. INTEGRATED CIRCUIT LAYOUT DESIGN RULE DECK CHECK TOOL AND CHECK METHOD [P] . WO2021249129A1 . 2021-12-16

  机译： 集成电路布局设计规则甲板检查工具和检查方法

• 1. A New Design and Implementation of an Attendance Checking Node for Coal Mines [J] . XIA Shi-xiong, QIAO Da-lei, CHEN Dai, 矿业科学技术（英文版） . 2007,第002期
• 2. A New Design and Implementation of an Attendance Checking Node for Coal Mines [J] . XIA, Shi-xiong, QIAO, 中国矿业大学学报：英文版 . 2007,第002期
• 3. The Design of Circuit for Checking Short in HT-7U Superconducting Tokamak Device [J] . 刘大海, 陈灼民, 武松涛 等离子体科学和技术：英文版 . 2000,第003期
• 4. 3D reconstruction method and connectivity rules of fracture networks generated under different mining layouts [J] . Zhang Ru, Ai Ting, Li Hegui, 矿业科学技术（英文版） . 2013,第006期
• 5. An edge-endpoint-based configurable hardware architecture for VLSI layout Design Rule Checking [J] . Luo Z., Ashar P., Martonosi M. VLSI Design . 2000,第3期
• 6. An Edge-endpoint-based Configurable HardwareArchitecture for VLSI Layout Design Rule Checking [J] . ZhenLuo, MargaretMartonosi, PranavAshar VLSI Design . 2000,第3期
• 7. Two-dimensional IC layout compaction based on topological design rule checking [J] . Valainis J., Kaptanoglu S. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 1990,第3期
• 8. Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking [C] . McGrath E.J., Whitney T. Wireless Broadband Conference, 2006 . 2006
• 9. Layout extraction including substrate parasitics for ESD protection circuits and design rule checking. [D] . Li, Qiao. 2001
• 10. PIM-Check: development of an international prescription-screening checklist designed by a Delphi method for internal medicine patients [O] . Aude Desnoyer, Anne-Laure Blanc, Valérie Pourcher, 2017
• 11. Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking [O] . Lars Liebmann, Jennifer Lund, Fook-luen Heng, 2001
• 12. General Design Rules for the Construction of m-Out-of-n Totally Self-Checking Checkers. [R] . smith,james e. metze, gernot 1975

• 1. Spatial Topology Rule Checking Algorithm of Linear Entity Based on Quadtree [J] . Shunping ZHOU ,Shaohuai CHEN ,Bo WAN . 地理信息系统（英文） . 2009,第1期
• 2. 一个分级几何设计规则检查器LSIS-ⅢHDRC的设计实现 [C] . 崔斌 . 全国第六届IC CAD学术年会 . 1991
• 3. 图形处理器平台上的超大规模集成电路设计规则检查加速 [A] . 池凤彬 . 2007