首页> 外国专利> METHOD OF FABRICATING THREE-DIMENSIONAL GATE-ALL-AROUND VERTICAL GATE STRUCTURES AND SEMICONDUCTOR DEVICES, AND THREE-DIMENSIONAL GATE-ALL-AROUND VERTICAL GATE STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF

METHOD OF FABRICATING THREE-DIMENSIONAL GATE-ALL-AROUND VERTICAL GATE STRUCTURES AND SEMICONDUCTOR DEVICES, AND THREE-DIMENSIONAL GATE-ALL-AROUND VERTICAL GATE STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF

机译：制作三维全围垂直门结构和半导体器件的方法，以及三维全围垂直门结构和半导体器件的方法

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摘要

Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure comprising providing a substrate; forming a plurality of layers having alternating first insulative material layers and second insulative material layers over the substrate; identifying bit line and word line locations for the formation of bit lines and word lines; removing at least a portion of the plurality of layers outside of the identified bit line and word line locations, each of the removed portions extending through the plurality of layers to at least a top surface of the substrate; forming a vertical first insulative material structure in the removed portions; performing an isotropic etching process to remove the second insulative material from the second insulative material layers; forming bit lines in the second insulative material layers within the identified bit line locations; and forming word lines in the identified word line locations.

机译：本示例实施例总体上涉及制造三维环绕栅（GAA）垂直栅（VG）半导体结构的方法，该方法包括提供衬底;在基板上形成具有交替的第一绝缘材料层和第二绝缘材料层的多个层;识别位线和字线的位置以形成位线和字线;去除所识别的位线和字线位置之外的多层的至少一部分，每个被去除的部分延伸穿过多层，直到至少衬底的顶表面;在去除部分中形成垂直的第一绝缘材料结构;进行各向同性蚀刻工艺，以从第二绝缘材料层中去除第二绝缘材料。在所确定的位线位置内的第二绝缘材料层中形成位线;在所识别的字线位置中形成字线。

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公开/公告号US2016284725A1

专利类型
公开/公告日2016-09-29

原文格式PDF
申请/专利权人 MACRONIX INTERNATIONAL CO. LTD.;
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申请/专利号US201514666703
发明设计人 TA-HONE YANG;
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申请日2015-03-24
分类号H01L27/115;H01L21/31;H01L21/66;H01L21/311;H01L23/528;H01L21/28;H01L21/3213;H01L29/792;H01L29/423;H01L29/66;H01L21/768;
国家 US
入库时间 2022-08-21 14:35:44

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