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Multi-core processor system, control method of the multi-core processor systems, and multi-core processor system control program of

机译:多核处理器系统,多核处理器系统的控制方法以及多核处理器系统的控制程序

摘要

PROBLEM TO BE SOLVED: To avoid access contention.;SOLUTION: A multi-core processor system 100 includes a memory controller 202 provided with a plurality of ports, and a shared memory 201 provided with a physical address space divided in each port. A CPU #1 acquires the number of CPUs for allocating execution object software to be executed by the multi-core processor system 100 from a parallelism information table 401 by an acquisition unit 402. After the acquisition, the CPU #1 determines a CPU for allocating the execution object software by a determination unit 403, and sets a physical address space corresponding to a logical address space regulated with the execution object software by a setting unit 404 for each CPU. After setting, the CPU #1 notifies an address converter 204 of an address to notify the execution object software of an execution start.;COPYRIGHT: (C)2014,JPO&INPIT
机译:解决的问题:为了避免访问争用。解决方案:多核处理器系统100包括具有多个端口的存储器控​​制器202,以及具有在每个端口中划分的物理地址空间的共享存储器201。 CPU#1通过获取单元402从并行性信息表401中获取用于分配要由多核处理器系统100执行的执行对象软件的CPU的数量。获取之后,CPU#1确定用于分配的CPU。由确定单元403执行对象软件,并为每个CPU设置与由设置单元404用执行对象软件调节的逻辑地址空间相对应的物理地址空间。设置之后,CPU#1将地址通知地址转换器204,以将执行开始通知执行对象软件。版权所有:(C)2014,JPO&INPIT

著录项

  • 公开/公告号JP5817860B2

    专利类型

  • 公开/公告日2015-11-18

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20140021650

  • 发明设计人 山下 浩一郎;早川 文彦;

    申请日2014-02-06

  • 分类号G06F9/50;

  • 国家 JP

  • 入库时间 2022-08-21 14:40:43

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