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Decoding circuit and method for improved performance and lower error floors of block-wise concatenated BCH codes with cyclic shift of constituent BCH codes
Decoding circuit and method for improved performance and lower error floors of block-wise concatenated BCH codes with cyclic shift of constituent BCH codes
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机译：具有组成BCH码的循环移位的按块级联的BCH码的改进的性能和较低的错误下限的解码电路和方法
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摘要
A decoding method of the present invention includes the steps of: reading the coded data according to the block-unit concatenation BCH encoding method from a non-volatile memory and conducting a hard-decision decoding operation for the read data; extracting a message block including an error in response to a hard-decision decoding failure; acquiring a first index which is the index of a row code word corresponding to the message block including the error and a second index which is the index of a column code word; calculating the respective polynomials of the code words failed to be decoded based on the first and second indexes; and correcting the errors using the calculated polynomials.
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