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Multi-compartment neuron suitable for implementation in a distributed hardware model by reducing communication bandwidth
Multi-compartment neuron suitable for implementation in a distributed hardware model by reducing communication bandwidth
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机译:通过减少通信带宽,适合在分布式硬件模型中实现的多隔室神经元
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摘要
Embodiments of the present invention provide a neural module comprising a multilevel hierarchical structure of neural compartments. Each neural compartment is interconnected to one or more neural compartments of a previous level and a next hierarchical level in the hierarchical structure. Each neural compartment integrates spike signals from interconnected neural compartments of a previous hierarchical level, generates a spike signal in response to the integrated spike signals reaching a threshold of said neural compartment, and delivers a generated spike signal to interconnected neural compartments of a next hierarchical level. Each neural compartment is further interconnected to one or more external spiking systems, such that said neural compartment integrates spike signals from interconnected external spiking systems, and delivers a generated spike signal to interconnected external spiking systems. The neural compartments of a neural module include one soma compartment and a plurality of dendrite compartments. Each neural compartment is excitatory or inhibitory.
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