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Time reference systems for CPU-based and optionally FPGA-based subsystems
Time reference systems for CPU-based and optionally FPGA-based subsystems
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机译：用于基于CPU和可选基于FPGA的子系统的时间参考系统
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摘要
A time reference system includes a master clock, generating a clock reference, interface logic and a CPU-based subsystem. The interface logic receives the clock reference and generates the clock, pulses, and timestamp signals. The CPU-based subsystem includes an internal counter, a CPU and a clock synthesizer, the CPU and receiving the pulses and timestamp signals. The clock synthesizer receives the clock signal and generates a CPU clock signal. Some examples include an FPGA-based subsystem having an FPGA-based card coupled to the interface logic for receipt of the clock, pulses and timestamp signals. In a method the timestamp value TO is generated by the CPU upon receipt of the timestamp signal. Upon receipt by the CPU of the next pulse signal, a timestamp counter baseline value TSCO is generated so the CPU internal counter is calibrated to the clock signal.
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