Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA

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• 3. Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA [P] . 欧洲知识产权局专利： EP2743848A1 . 2014-06-18

  机译： 验证模块设备的调试软件和嵌入式处理器设计的时序超过单个FPGA的容量

• 4. VERIFICATION MODULE APPARATUS FOR DEBUGGING SOFTWARE AND TIMING OF AN EMBEDDED PROCESSOR DESIGN THAT EXCEEDS CAPACITY OF SINGLE FIELD PROGRAMMABLE GATE ARRAY (FPGA) [P] . 日本专利： JP2014120155A . 2014-06-30

  机译： 用于调试软件的验证模块设备和嵌入式处理器设计的时序超过单场可编程门阵列（FPGA）的能力

• 5. Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA [P] . 美国专利： US2014013163A1 . 2014-01-09

  机译： 验证模块设备的调试软件和嵌入式处理器设计的时序超过单个FPGA的容量

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