首页> 外国专利> NUMERICAL DETERMINATION CIRCUIT FOR MULTIVALUED LOGICAL CIRCUIT BASED ON PRINCIPLE OF HOOJI ALGEBRA, MULTIVALUED LOGICAL TWO-STAGE CONNECTIN CIRCUIT BASED ON PRINCIPLE OF HOOJI ALGEBRA HAVING FUNCTION FOR SUPPRESSING UNNECESSARY VIBRATION OF INPUT SIGNAL, AND MULTI-LEVEL POTENTIAL CLAMP MEANS

NUMERICAL DETERMINATION CIRCUIT FOR MULTIVALUED LOGICAL CIRCUIT BASED ON PRINCIPLE OF HOOJI ALGEBRA, MULTIVALUED LOGICAL TWO-STAGE CONNECTIN CIRCUIT BASED ON PRINCIPLE OF HOOJI ALGEBRA HAVING FUNCTION FOR SUPPRESSING UNNECESSARY VIBRATION OF INPUT SIGNAL, AND MULTI-LEVEL POTENTIAL CLAMP MEANS

机译：基于Hooji代数原理的多值逻辑电路的数值确定电路，基于Hooji代数原理的多值逻辑两级连接电路具有抑制不必要的输入点和输入点振动的功能

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摘要

PROBLEM TO BE SOLVED: To suppress voltage vibration, e.g., overshooting, occurring in the input section of a multivalued logical circuit based on the principle of Hooji algebra, i.e., Japan-born multivalued logic.;SOLUTION: Example: (One multilevel NOT circuit or a multilevel EVEN circuit connecting a pull resistor for pulling up or down the output potential to predetermined constant potentials when the output is open) and one clamp diode for clamping each input potential to each constant potential (with the lower one of a specific constant potential for output of a prestage circuit and the predetermined constant potential as the low potential side, and the higher one as the high potential side) for each post-stage circuit in a multivalued complete circuit where a plurality of two-stage connection circuits of multivalued AND circuit are connected in parallel. Consequently, each input voltage variation of each post-stage circuit can be suppressed. In this multivalued complete circuit (Multivalue logic completeness-of-completeness circuit), 2-3 kinds of basic multivalued logic circuit form a complete system.;COPYRIGHT: (C)2015,JPO&INPIT

机译：解决的问题：基于Hooji代数原理（即日本诞生的多值逻辑），抑制在多值逻辑电路的输入部分中发生的电压振动（例如，过冲）。解决方案：示例：（一个多电平NOT电路或多级EVEN电路，该电路连接一个拉电阻器，用于在输出打开时将输出电势上拉或下拉至预定的恒定电势;以及一个钳位二极管，用于将每个输入电势钳位至每个恒定电势（特定恒定电势中的较低者为一个用于多级完整电路中每个后级电路的前级电路的输出，并将预定的恒定电势作为低电势侧，将较高的一个作为高电势侧），其中多个多级AND的两级连接电路电路并联连接。因此，可以抑制每个后级电路的每个输入电压变化。在这个多值完整电路（多值逻辑完整性电路）中，有2-3种基本多值逻辑电路构成一个完整的系统。版权所有：（C）2015，JPO＆INPIT

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公开/公告号JP2015122743A

专利类型
公开/公告日2015-07-02

原文格式PDF
申请/专利权人 SUZUKI TOSHIYASU;
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申请/专利号JP20140238294
发明设计人 SUZUKI TOSHIYASU;
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申请日2014-11-25
分类号H03K19/20;
国家 JP
入库时间 2022-08-21 15:32:56

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