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TIMING OPTIMIZED IMPLEMENTATION OF ALGORITHM TO REDUCE SWITCHING RATE ON HIGH THROUGHPUT WIDE BUSES
TIMING OPTIMIZED IMPLEMENTATION OF ALGORITHM TO REDUCE SWITCHING RATE ON HIGH THROUGHPUT WIDE BUSES
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机译：优化算法的实现以降低高通量宽总线上的开关率
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摘要
A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup circuit to generate majority data output. An inversion control circuit receives the majority data output, retrieves feedback data from a preceding inversion control output and interprets the two data to generate inversion control signal, which is used to perform inversion control on data along the data path before being communicated to the receiver. The inversion control signal is used by the receiver to interpret the data received from the data path.
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