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CLOCK NETWORK FISHBONE ARCHITECTURE FOR A STRUCTURED ASIC MANUFACTURED ON A 28 NM CMOS PROCESS LITHOGRAPHIC NODE
CLOCK NETWORK FISHBONE ARCHITECTURE FOR A STRUCTURED ASIC MANUFACTURED ON A 28 NM CMOS PROCESS LITHOGRAPHIC NODE
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机译：在28 NM CMOS工艺光刻节点上制造的结构化ASIC的时钟网络鱼骨架构
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摘要
A clock architecture for a Structured ASIC chip, manufactured using a CMOS process is shown. A via-configurable logic block (VCLB) architecture in the Structured ASIC has a core region containing memory and logic cells arranged in columns that are supplied by a clock network having a global clock network tree and a low-level clock mesh to distribute the global clock signal in a repeating pattern. The clock mesh has a fishbone configuration in outline and allows for scalable expansion of the clock network. In one embodiment 36 global clocks may be provided to the Structured ASIC, with four clocks per logic cell. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node, having several metal layers but preferably is programmable on a single via layer.
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