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Memory device having sensing circuitry with automatic latching of sense amplifier output node
Memory device having sensing circuitry with automatic latching of sense amplifier output node
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机译：具有感应电路的存储设备，感应电路具有感应放大器输出节点的自动锁存功能
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摘要
A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to bitlines associated with respective columns of the memory cells of the memory array. The sensing circuitry comprises, for at least a given one of the bitlines of the memory array, a sense amplifier configured to sense data on the given bitline, with the sense amplifier having at least one internal node and at least one output node. The sensing circuitry further comprises a latch circuit having a data input coupled to the output node and a control input coupled to the internal node, with the latch circuit being configured to latch sensed data from the output node responsive to a signal at the internal node.
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