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Schottky barrier quantum well resonant tunneling transistor

机译:肖特基势垒量子阱共振隧穿晶体管

摘要

A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 Å. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.
机译:半导体晶体管器件包括一个或多个导电基极区,第一半导体势垒区,第二半导体势垒区,导电发射极区和导电集电极区。第一半导体势垒区或第二半导体势垒区的尺寸小于100&。第一肖特基势垒结形成在第一半导体势垒区和一个或多个导电基极区的界面处。第二肖特基势垒结形成在第二半导体势垒区和一个或多个导电基极区的界面处。第三肖特基势垒结形成在导电发射极区和第一半导体势垒区的界面处。第四肖特基势垒结形成在导电集电极区和第二半导体势垒区的界面处。

著录项

  • 公开/公告号JP5368252B2

    专利类型

  • 公开/公告日2013-12-18

    原文格式PDF

  • 申请/专利权人 ウ;コ-チェン;

    申请/专利号JP20090245103

  • 发明设计人 ウ;コ-チェン;

    申请日2009-10-26

  • 分类号H01L21/331;H01L29/73;H01L21/28;H01L29/417;

  • 国家 JP

  • 入库时间 2022-08-21 16:12:31

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