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Control manner null of the phase simulation looping circuit and the phase simulation looping

机译:相位仿真回路和相位仿真回路的控制方式为零

摘要

PROBLEM TO BE SOLVED: To provide a PLL circuit and the like suppressing the increase of chip size, and having a wide oscillation frequency band.SOLUTION: A VCO 34 produces an output clock signal CLKO having oscillation frequency fVCO according to control voltage TV. A PLL block 2 produces the control voltage VT. A lock detector 24 detects whether the oscillation frequency fVCO is locked by setting frequency fS or not. A VT voltage detecting portion 31 decides to select any one of varactors VA1-VA3. A selector portion 32 selects a varactor VA0 in a rough adjustment stage of the output clock signal CLKO. The rough adjustment stage is shifted to a fine adjustment stage according to receiving that locking is detected in the rough adjustment stage from the lock detector 24. In the fine adjustment stage, the selection of the varactor selected by the VT voltage detecting portion 31 at the time of shifting is kept.
机译:解决的问题:提供一种抑制芯片尺寸增加并且具有宽振荡频带的PLL电路等。解决方案:VCO 34根据控制电压TV产生具有振荡频率fVCO的输出时钟信号CLKO。 PLL块2产生控制电压VT。锁定检测器24通过设定频率fS来检测振荡频率fVCO是否被锁定。 VT电压检测部分31决定选择变容二极管VA1-VA3中的任何一个。选择器部分32在输出时钟信号CLKO的粗调阶段中选择变容二极管VA0。根据从锁定检测器24接收到在粗调阶段中检测到锁定的信号,将粗调阶段移至微调阶段。在微调阶段,由VT电压检测部分31在选择器处选择变容二极管。保持换档时间。

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