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Control manner null of the phase simulation looping circuit and the phase simulation looping
Control manner null of the phase simulation looping circuit and the phase simulation looping
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机译:相位仿真回路和相位仿真回路的控制方式为零
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摘要
PROBLEM TO BE SOLVED: To provide a PLL circuit and the like suppressing the increase of chip size, and having a wide oscillation frequency band.SOLUTION: A VCO 34 produces an output clock signal CLKO having oscillation frequency fVCO according to control voltage TV. A PLL block 2 produces the control voltage VT. A lock detector 24 detects whether the oscillation frequency fVCO is locked by setting frequency fS or not. A VT voltage detecting portion 31 decides to select any one of varactors VA1-VA3. A selector portion 32 selects a varactor VA0 in a rough adjustment stage of the output clock signal CLKO. The rough adjustment stage is shifted to a fine adjustment stage according to receiving that locking is detected in the rough adjustment stage from the lock detector 24. In the fine adjustment stage, the selection of the varactor selected by the VT voltage detecting portion 31 at the time of shifting is kept.
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