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On the production mannered null high

机译:对生产的态度虚高

摘要

PROBLEM TO BE SOLVED: To provide a manufacturing method of a super junction semiconductor device having a super junction structure including parallel pn layers, that can be manufactured at low cost with improved production efficiency by reducing thermal diffusion time and the number of steps needed for making the parallel pn layers serving as drift layers successive impurity diffusion regions.;SOLUTION: A manufacturing method of a super junction semiconductor device comprises a first step of growing an epitaxial layer 3 on a high-concentration semiconductor substrate 1 with a first conductivity type, a second step of implanting ions of an impurity element with the first conductivity type whose diffusion coefficient is higher than that of boron and implanting boron ions twice or more at different acceleration voltages, a third step of increasing the thickness of the epitaxial layer to a predetermined layer thickness by repeating the first and second steps, and a fourth step of forming parallel pn layers 10 in which impurities are successive in a direction perpendicular to a main plane of the substrate and which are mutually adjacent in a direction parallel to the main plane.;COPYRIGHT: (C)2012,JPO&INPIT
机译:解决的问题:提供一种具有包括平行的pn层的超结结构的超结半导体器件的制造方法,该方法可以通过减少热扩散时间和制造所需的步骤数来以低成本制造,并且具有提高的生产效率。解决方案:超结半导体器件的制造方法包括第一步,即在具有第一导电类型的高浓度半导体衬底1上生长外延层3的第一步。第二步骤是注入扩散系数高于硼的第一导电类型的杂质元素的离子,并在不同的加速电压下注入两次或更多次硼离子,第三步骤是将外延层的厚度增加到预定的厚度通过重复第一和第二步骤以及形成p的第四步骤的厚度芳纶pn层10,其中杂质在垂直于基板主平面的方向上连续并且在平行于主平面的方向上彼此相邻。;版权所有:(C)2012,JPO&INPIT

著录项

  • 公开/公告号JP5556335B2

    专利类型

  • 公开/公告日2014-07-23

    原文格式PDF

  • 申请/专利权人 富士電機株式会社;

    申请/专利号JP20100101944

  • 发明设计人 桐沢 光明;

    申请日2010-04-27

  • 分类号H01L29/78;H01L21/336;H01L29/06;

  • 国家 JP

  • 入库时间 2022-08-21 16:14:45

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