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Identification circuit for creating unique identification pattern for integrated circuit, has circuitry ring whose switching stages are selected from respective unstable states in response to challenge word selected signal delays
Identification circuit for creating unique identification pattern for integrated circuit, has circuitry ring whose switching stages are selected from respective unstable states in response to challenge word selected signal delays
The circuit (1) has bi-stable closed-circuit ring (2) consisting multiple switching stages (3-1-3-4), where each switching stage of the circuit ring comprises two parallel internal signal delay paths that are connected to an input side directly. A reset element is provided for each switching stage of the circuit ring. The switching stages of the circuitry ring are selected from respective unstable states in response to by-scale challenge word selected signal delays that are proceeded in stable states to form a unique identification pattern for an object to be identified. An independent claim is also included for an identification tag for identifying a physical object to be identified with an identification circuit.
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