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PATTERN FORMATION METHOD OF A SEMICONDUCTOR DEVICE WHICH IMPORVES CRITICAL DIMENSION UNIFORMITY OF A PATTERN

机译:改善图案临界尺寸均匀性的半导体装置的图案形成方法

摘要

PURPOSE: A pattern forming method of a semiconductor device is provided to prevent an SOC film to be lifted in the strip process of an amorphous carbon layer before etching an etched layer by eliminating the SOC film remaining in a peripheral circuit region.;CONSTITUTION: An etched layer(200), a first hard mask(205) and a second hard mask(210) are formed on the upper side of a semiconductor substrate which includes a cell region and a peripheral circuit region. A second hard mask pattern(210a) of a line-shape is formed by patterning the second hard mask of the cell region. A third hard mask pattern(215a) of the line-shape which is crossed with the second hard mask pattern is formed on the upper side of the first hard mask. The first hard mask is partly etching using the second hard mask pattern and the third hard mask pattern as an etching mask. A first hard mask pattern is formed by etching the first hard mask which is partly etched.;COPYRIGHT KIPO 2013
机译:目的:提供一种半导体器件的图案形成方法,以通过消除残留在外围电路区域中的SOC膜,防止在蚀刻蚀刻层之前在非晶碳层的剥离工艺中抬高SOC膜。在包括单元区域和外围电路区域的半导体衬底的上侧上形成蚀刻层(200),第一硬掩模(205)和第二硬掩模(210)。通过图案化单元区域的第二硬掩模来形成线形的第二硬掩模图案(210a)。与第二硬掩模图案交叉的线形的第三硬掩模图案(215a)形成在第一硬掩模的上侧。使用第二硬掩模图案和第三硬掩模图案作为蚀刻掩模来部分蚀刻第一硬掩模。通过蚀刻部分被蚀刻的第一硬掩模来形成第一硬掩模图案。; COPYRIGHT KIPO 2013

著录项

  • 公开/公告号KR20120126717A

    专利类型

  • 公开/公告日2012-11-21

    原文格式PDF

  • 申请/专利权人 SK HYNIX INC.;

    申请/专利号KR20110044734

  • 发明设计人 LEE KI LYOUNG;SHIM HYUN KYUNG;

    申请日2011-05-12

  • 分类号H01L21/027;

  • 国家 KR

  • 入库时间 2022-08-21 16:28:40

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