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Integrated framework for finite-element methods for package, device and circuit co-design

机译:用于封装,器件和电路协同设计的有限元方法的集成框架

摘要

Electrical finite element analysis is carried out on a circuit design, which includes devices, to determine an acceptable power-performance envelope and to obtain data for circuit temperature mapping. A circuit temperature map is developed for the circuit design, based on the data for circuit temperature mapping. Thermo-mechanical finite element analysis is carried out on a package design for the circuit design, based on the circuit temperature map, to determine a package reliability limit based on thermal stress considerations. It is determined whether the package design and the circuit design jointly satisfy: (i) power-performance conditions specified in the acceptable power-performance envelope; and (ii) the package reliability limit based on the thermal stress considerations.
机译:在电路设计(包括设备)上进行电有限元分析,以确定可接受的功率性能范围并获取用于电路温度映射的数据。基于电路温度映射的数据,为电路设计开发了电路温度映射。根据电路温度图,对用于电路设计的封装设计进行热机械有限元分析,以基于热应力考虑因素确定封装可靠性极限。确定封装设计和电路设计是否共同满足:(i)在可接受的功率性能范围内规定的功率性能条件; (ii)基于热应力考虑的封装可靠性极限。

著录项

  • 公开/公告号US8352230B2

    专利类型

  • 公开/公告日2013-01-08

    原文格式PDF

  • 申请/专利权人 KEUNWOO KIM;SOOJAE PARK;

    申请/专利号US20100723130

  • 发明设计人 KEUNWOO KIM;SOOJAE PARK;

    申请日2010-03-12

  • 分类号G06F17/50;G06G7/62;

  • 国家 US

  • 入库时间 2022-08-21 16:42:36

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