首页> 外国专利> NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH

NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH

机译:具有可变深度的垂直选择门的非易失性记忆细胞

摘要

The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.
机译:本公开涉及一种集成电路,该集成电路包括:至少两个形成在半导体衬底中的存储单元;以及与该存储单元的选择晶体管共用的掩埋栅。掩埋栅极具有在选择晶体管的垂直沟道区域的前面延伸的第一深度的第一部分,以及比第一深度大的第二深度的至少第二部分,该第二深度穿透到掩埋的源极线中。掩埋栅极的下侧被形成选择晶体管的源极区域并到达掩埋源极线的掺杂区域所边界,在该水平处,掩埋栅极的第二部分穿透到掩埋源极线中,从而该源极区域为耦合到掩埋的源极线。

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