A high-level synthesis device, which converts a behavior description file describing a function of an integrated circuit using a high-level language without timing description, into a hardware description file describing the integrated circuit including timing description, has: a processor; a high-level synthesis unit in which the processor converts a behavior description file having a functional portion describing the function and a control portion controlling timing, into a first hardware description file; a variable extraction unit; a loop information generation unit; a static latency extraction unit; a latency calculation circuit generation unit in which the processor generates a second hardware description file describing a latency calculation circuit which generates the latency information based on loop count and static latency; and an insertion unit in which the processor inserts the second hardware description file into the first hardware description file to generate a third hardware description file.
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