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How to manage coherency in a multiprocessor data processing system having a cache memory of the lower level and one cache memory of several high-level, and data processing system
How to manage coherency in a multiprocessor data processing system having a cache memory of the lower level and one cache memory of several high-level, and data processing system
According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
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