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FRACTIONAL-N PHASE LOCKED LOOP CAPABLE OF GENERATING AN EXACT PHASE CLOCK SIGNAL, A METHOD THEREOF, AND APPARATUSES INCLUDING THE SAME
FRACTIONAL-N PHASE LOCKED LOOP CAPABLE OF GENERATING AN EXACT PHASE CLOCK SIGNAL, A METHOD THEREOF, AND APPARATUSES INCLUDING THE SAME
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机译：能够产生精确相位时钟信号的分数n相锁相环，其方法以及包括该相位锁相环的装置
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摘要
PURPOSE: A fractional-n phase locked loop, a method thereof, and apparatuses including the same are provided to obtain a wide frequency synthesis domain by using a secondary sigma-DELTA modulator.;CONSTITUTION: A phase control circuit(20) detects the difference of the phase of a reference clock signal and the phase of a feedback clock signal. The phase control circuit outputs a plurality of phase clock signals in response to a detected difference. A phase selector(30) outputs one of the plurality of phase clock signals outputted from the phase control circuit as the phase clock signal in response to a phase selection signal. A control circuit(40) generates the phase selection signal by using a sigma-DELTA modulator operation clock signal. A first divider(90) generates the feedback clock signal by dividing the phase clock signal to an integer.;COPYRIGHT KIPO 2012
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