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Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool
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机译：使用临界面积分析工具计算VLSI设计对随机缺陷和系统缺陷的敏感性的方法
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摘要
A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.
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