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Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level
Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level
A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.
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