首页>
外国专利>
Method and system for transforming fork-join blocks in a hardware description language (HDL) specification
Method and system for transforming fork-join blocks in a hardware description language (HDL) specification
展开▼
机译：在硬件描述语言（HDL）规范中转换fork-join块的方法和系统
展开▼
页面导航
摘要
著录项
相似文献
摘要
The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications in the simulation kernel. This transformation is done in such a way that the parallel behavior is retained in its entirety, and the same simulation time-relative results are produced. The concept of concurrency of processes inherent in HDL languages, including System Verilog, is utilized to achieve the same simulation results via the transformed HDL code, which uses the non-parallel block subset of System Verilog HDL.
展开▼
