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Distributed User Controlled Multilevel Block and Global Cache Coherence with Accurate Completion Status

机译:具有准确完成状态的分布式用户控制的多级块和全局缓存一致性

摘要

This invention permits user controlled cache coherence operations with the flexibility to do these operations on all levels of cache together or each level independently. In the case of an all level operation, the user does not have to monitor and sequence each phase of the operation. This invention also provides a way for users to track completion of these operations. This is critical for multi-core/multi-processor devices. Multiple cores may be accessing the end point and the user/application needs to be able to identify when the operation from one core is complete, before permitting other cores access that data or code.
机译:本发明允许用户控制的高速缓存一致性操作具有灵活性,以一起或单独地在所有高速缓存的各个级别上进行这些操作。在全级别操作的情况下,用户不必监视操作的每个阶段并对其进行排序。本发明还为用户提供了一种跟踪这些操作完成的方式。这对于多核/多处理器设备至关重要。多个内核可能正在访问端点,并且用户/应用程序需要能够在允许其他内核访问该数据或代码之前,识别来自一个内核的操作何时完成。

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