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Robust design identification and robust design improvement using static timing analysis
Robust design identification and robust design improvement using static timing analysis
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机译：使用静态时序分析进行稳健的设计识别和稳健的设计改进
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摘要
Statistical timing analysis techniques can be used to lead to the construction of robust circuits in a consistent manner through the entire design flow of synthesis, placement and routing. An exemplary technique can include receiving library data for a design including timing models. By comparing implementations of this data, a robust circuit can be defined based on a set of criteria, which can include worst negative slack, endpoint slack distribution, timing constraint violations, and total negative slack. At this point, statistical timing analysis can be used to drive logic changes that generate improved robustness in the design. The statistical timing analysis can use a static timing delay associated with the arc in statistical timing analysis as a mean and a specified percentage of the mean as the standard deviation.
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