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Being the high density MOS gate die device which possesses with the higher stratum of society where

机译:作为具有较高社会阶层的高密度MOS栅极器件

摘要

A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type. A doped well region of a second and opposite conduction type is formed in an upper surface of the upper layer, and a dopant of the first conduction type is implanted in the well region to form a heavily doped source region. A layer of nitride is formed on the upper surface of the upper layer, and the nitride layer and upper layer are selectively etched, thereby forming a trench in the upper layer. The trench is lined with an insulating layer, then filled with a conductive material to form a trench gate. The nitride layer is removed, and a layer of interlevel dielectric material is formed on the trench gate and the upper surface of the upper layer. The interlevel dielectric layer is selectively etched, thereby forming a source region contact area. The source region is selectively etched to form a shallow recess that provides a body region contact area. A dopant of the second conduction type is implanted into the recess, thereby forming a deep body region underlying the recess.
机译:一种高密度MOS门控器件,包括半导体衬底和设置在该衬底上的第一导电类型的掺杂上层。上层在上表面处包括第一导电类型的重掺杂源极区域和第二导电类型和相反导电类型的掺杂阱区。包括用于源极区域的接触区域的上表面还包括凹入部分,该凹入部分包括在凹入部分下面的上层中用于第二导电类型的重掺杂深体区域的接触区域。该器件还包括设置在上层中的沟槽栅极,该沟槽栅极包括通过绝缘层与上层隔开的导电材料。一种形成高密度MOS栅控器件的工艺,包括提供包括第一导电类型的掺杂的上层的半导体衬底。在上层的上表面中形成第二导电类型和相反导电类型的掺杂阱区域,并且第一导电类型的掺杂剂被注入到阱区域中以形成重掺杂的源极区域。在上层的上表面上形成氮化物层,并且选择性地蚀刻氮化物层和上层,从而在上层中形成沟槽。沟槽衬有绝缘层,然后填充导电材料以形成沟槽栅极。去除氮化物层,并且在沟槽栅极和上层的上表面上形成层间介电材料层。层间电介质层被选择性地蚀刻,从而形成源极区接触区域。选择性地蚀刻源极区域以形成提供主体区域接触区域的浅凹部。将第二导电类型的掺杂剂注入到凹槽中,从而在凹槽下方形成深体区域。

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