首页> 外国专利> GATED DIODE HAVING AT LEAST ONE LIGHTLY-DOPED DRAIN (LDD) IMPLANT BLOCKED AND CIRCUITS AND METHODS EMPLOYING SAME

GATED DIODE HAVING AT LEAST ONE LIGHTLY-DOPED DRAIN (LDD) IMPLANT BLOCKED AND CIRCUITS AND METHODS EMPLOYING SAME

机译:至少有一个轻度漏水(LDD)植入物阻塞的门控二极管和采用相同方法的电路和方法

摘要

Gated diodes, manufacturing methods, and related circuits are provided wherein at least one lightly-doped drain (LDD) implant is blocked in the gated diode to reduce its capacitance. In this manner, the gated diode may be used in circuits and other applications whose performance is sensitive to load capacitance while still obtaining the performance characteristics of a gated diode. These characteristics include fast turn-on times and high conductance, making the gated diodes disclosed herein well-suited for electro-static discharge (ESD) protection circuits as one application example. The examples of the gated diode disclosed herein include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region, wherein a P-N junction is formed. At least one LDD implant is blocked in the gated diode to reduce capacitance.
机译:提供了门控二极管,制造方法和相关电路,其中至少一个轻掺杂漏极(LDD)注入被阻挡在门控二极管中以减小其电容。以这种方式,门控二极管可以用于其性能对负载电容敏感的电路和其他应用中,同时仍然获得门控二极管的性能特征。这些特性包括快速导通时间和高电导率,这使得本文所公开的栅极二极管非常适合作为一个应用实例的静电放电(ESD)保护电路。本文公开的门控二极管的示例包括具有阱区和其上的绝缘层的半导体衬底。在绝缘层上方形成栅电极。在阱区域中提供阳极和阴极区域,其中形成P-N结。至少一个LDD注入被阻挡在门控二极管中,以减小电容。

著录项

  • 公开/公告号WO2010105178A3

    专利类型

  • 公开/公告日2011-01-13

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;WORLEY EUGENE R.;

    申请/专利号WO2010US27172

  • 发明设计人 WORLEY EUGENE R.;

    申请日2010-03-12

  • 分类号H01L29/861;H01L23/60;

  • 国家 WO

  • 入库时间 2022-08-21 18:00:44

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