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METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
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机译:运用分层分层设计流程设计集成电路的方法和采用该方法的装置
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摘要
Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor.
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