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With record media, and the design rule verification device null specified frame of reference which record the design rule

机译:使用记录介质,并且设计规则验证设备将记录设计规则的指定参考框架为空

摘要

PROBLEM TO BE SOLVED: To efficiently shorten a verification period even though a design rule is complicated.;SOLUTION: Layout data 200 is diagram information representing objects, such as wirings constituting a semiconductor circuit, a viahole and a power source circuit. The layout data 200 concretely has object form data 201 showing objects and representative form data 202. This design rule verifying apparatus 300 includes an acquiring part 301, a verifying part 302 and an outputting part 303. The acquiring part 301 acquires the representative form data 202 represented by using representative points of an object in the semiconductor circuit from the layout data 200 on the semiconductor circuit. The verifying part 302 verifies whether the layout data 200 violates a design rule 310 on the basis of the representative form data 202 acquired by the acquiring part 301. The outputting part 303 outputs a verification output verified by the verifying part 302.;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:即使设计规则复杂,也要有效地缩短验证周期。解决方案:布局数据200是表示对象的图形信息,例如构成半导体电路,过孔和电源电路的布线。布局数据200具体地具有表示对象的对象形式数据201和代表形式数据202。该设计规则验证装置300包括获取部分301,验证部分302和输出部分303。获取部分301获取代表形式数据202。通过使用来自半导体电路上的布局数据200的半导体电路中的对象的代表点来表示。验证部302基于由获取部301获取的代表表格数据202,验证布局数据200是否违反设计规则310。输出部303输出由验证部302验证的验证输出。 C)2009,日本特许厅

著录项

  • 公开/公告号JP4659892B2

    专利类型

  • 公开/公告日2011-03-30

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20090108132

  • 发明设计人 松岡 英俊;

    申请日2009-04-27

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 18:17:58

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