首页>
外国专利>
APPARATUS AND A METHOD FOR ENCODING A HIGH SPEED QUASI-CYCLIC LOW DENSITY PARITY CHECK CODE WITH LOW COMPLEXITY, CAPABLE OF REDUCING THE COMPLEXITY OF A HARDWARE PART
APPARATUS AND A METHOD FOR ENCODING A HIGH SPEED QUASI-CYCLIC LOW DENSITY PARITY CHECK CODE WITH LOW COMPLEXITY, CAPABLE OF REDUCING THE COMPLEXITY OF A HARDWARE PART
展开▼
机译：低复杂度地编码高速准循环低密度奇偶校验码的装置和方法，能够降低硬件零件的复杂度
展开▼
页面导航
摘要
著录项
相似文献
摘要
PURPOSE: An apparatus and a method for encoding a high speed quasi-cyclic low density parity check(QC-LDPC) code with low complexity are provided to obtain linear complexity by performing an encoding operation directly using a parity check matrix.;CONSTITUTION: A parity bit generating unit(440) is generates a parity bit. A temporary parity bit generating unit(410) generates input information with circulants. A temporary bit generating unit corresponds each circulant to each line using the parity bit. A correction bit generating unit(420) corrected parity bit using the output of the temporary parity bit generating unit. A parity bit correcting unit(430) corrects the parity bit by reflecting the output of the correction bit generating unit to the temporary parity bit generating unit.;COPYRIGHT KIPO 2010
展开▼
