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DISTURBANCE DETECTION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, DISTURBANCE DETECTION METHOD, AND TEST METHOD
DISTURBANCE DETECTION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, DISTURBANCE DETECTION METHOD, AND TEST METHOD
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机译：干扰检测电路，半导体集成电路，干扰检测方法和测试方法
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摘要
A disturbance detection circuit is provided with a system in which a plurality of disturbance detection logic gates (G1 to Gn) each of which changes the logic value of the output in response to occurrence of a disturbance within the circuit and changes the logic value of the output to the next stage in response to a change in the logic value of the input from the previous stage are connected in series. The disturbance detection circuit is configured in such a manner that a constant logic value is inputted to the first-stage disturbance detection logic gate (G1) among the disturbance detection logic gates and that the occurrence of a disturbance is detected by the change in the logic value of the output of the disturbance detection logic gate (Gn) in the last-stage among the disturbance detection logic gates.
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