首页> 外国专利> Correction method and correction system for design data or mask data, validation method and validation system for design data or mask data, yield estimation method for semiconductor integrated circuit, method for improving design rule, mask production method, and semiconductor integrated circuit production method

Correction method and correction system for design data or mask data, validation method and validation system for design data or mask data, yield estimation method for semiconductor integrated circuit, method for improving design rule, mask production method, and semiconductor integrated circuit production method

机译：设计数据或掩模数据的校正方法和校正系统，设计数据或掩模数据的验证方法和验证系统，半导体集成电路的成品率估计方法，改进设计规则的方法，掩模生产方法和半导体集成电路生产方法

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摘要

A validation/correction method is provided for design data or mask data by which a pattern which becomes critical in a process is extracted in advance so that the pattern can be corrected. Consequently, the process spec is achieved in a short period of time after OPC or process proximity effect correction (PPC).

机译：提供一种用于设计数据或掩模数据的验证/校正方法，通过该方法可以预先提取在处理中变得至关重要的图案，从而可以校正该图案。因此，在OPC或过程邻近效应校正（PPC）之后的短时间内即可达到过程规范。

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公开/公告号US7735053B2

专利类型
公开/公告日2010-06-08

原文格式PDF
申请/专利权人 KATSUHIKO HARAZAKI;
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申请/专利号US20070819397
发明设计人 KATSUHIKO HARAZAKI;
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申请日2007-06-27
分类号G06F17/50;
国家 US
入库时间 2022-08-21 18:47:58

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