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Reducing memory access latency for hypervisor- or supervisor-initiated memory access requests
Reducing memory access latency for hypervisor- or supervisor-initiated memory access requests
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机译：减少系统管理程序或管理程序启动的内存访问请求的内存访问延迟
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摘要
A computer-implemented method, data processing system, and computer usable program code are provided for reducing memory access latency. A memory controller receives a memory access request and determines if an address associated with the memory access request falls within an address range of a plurality of paired memory address range registers. The memory controller determines if an enable bit associated with the address range is set to 1 in response to the address falling within one of the address ranges. The memory controller flags the memory access request as a high-priority request in response to the enable bit being set to 1 and places the high-priority request on a request queue.;A dispatcher receives an indication that a memory bank is idle. The dispatcher determines if high-priority requests are present in the request queue and, if so, sends the earliest high-priority request to the idle memory bank.
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