首页> 外国专利> Implementing a user design in a programmable logic device with single event upset mitigation

Implementing a user design in a programmable logic device with single event upset mitigation

机译:借助单事件击穿缓解功能在可编程逻辑器件中实现用户设计

摘要

Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, a software portion of the design is compiled into software that is executable by a hard processor disposed on a single semiconductor chip with resources of an programmable logic device (PLD). A first synthesized version of a hardware portion of the design is generated for the PLD. A synthesized memory scrubber having an empty block for an address counter is generated, as well as a triple modular redundant (TMR) address counter. The memory in the first synthesized version of the hardware portion of the design is replaced with the memory scrubber, and a complete set of netlists is generated, including a TMR hardware portion of the design and a single instance of the synthesized memory scrubber. A configuration bitstream is generated from the complete set of netlists and stored for later use.
机译:公开了用于生成电子电路设计的实现的各种方法。在一种方法中,将设计的软件部分编译为可由具有可编程逻辑器件(PLD)的资源的单个处理器芯片上的硬处理器执行的软件。为PLD生成设计的硬件部分的第一合成版本。生成具有用于地址计数器的空块的合成存储器清理器,以及三重模块冗余(TMR)地址计数器。设计的硬件部分的第一个合成版本中的存储器被替换为内存清理器,并生成了一组完整的网表,包括设计的TMR硬件部分和合成内存清理器的单个实例。配置比特流是从完整的网表集中生成的,并存储起来供以后使用。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号