A fast Fourier transform (FFT) computation system comprises a plurality of field programmable gate arrays (FPGAs), a plurality of initial calculations modules, a plurality of butterfly modules, a plurality of external interfaces, and a plurality of FPGA interfaces. The FPGAs may include a plurality of configurable logic elements that may be configured to perform mathematical calculations for the FFT. The initial calculations modules may be formed from the configurable logic elements and may be implemented according to a split-radix tree architecture that includes a plurality of interconnected nodes. The initial calculations modules may perform the initial split-radix calculations of the FFT. The butterfly modules may be formed from the configurable logic elements and may be implemented according to the split-radix tree architecture to perform at least a portion of the FFT computation in an order that corresponds to the connection of the nodes of the split-radix tree architecture. The FPGA interfaces are included in each FPGA and allow communication between the FPGAs. The external interfaces are also included in each FPGA and allow communication with one or more external devices in order to receive data which requires an FFT computation and to transmit the FFT computation results.
展开▼
