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Concurrently Modeling Delays Between Points in Static Timing Analysis Operation

机译:在静态时序分析操作中同时建模点之间的延迟

摘要

An apparatus, program product and method perform static timing analysis on an integrated circuit design by concurrently modeling a plurality of timing delays associated with a connection between points in the design. The delays are conveyed in multiple clock signals of a single timing run of a static timing analysis operation. Multiple paths comprising logical user defined delay segments are assigned different delays. Only one signal may be permitted to propagate along each path.
机译:一种设备,程序产品和方法,通过同时建模与设计中的点之间的连接相关联的多个时序延迟,来对集成电路设计执行静态时序分析。延迟以静态时序分析操作的单个时序运行的多个时钟信号传送。包括逻辑用户定义的延迟段的多个路径被分配了不同的延迟。只能允许一个信号沿每个路径传播。

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