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Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together

机译:可编程逻辑器件收发器体系结构,有助于一起使用各种数量的收发器通道

摘要

Transceiver circuitry on a programmable logic device integrated circuit (“PLD”) is preferably provided in a plurality of identical or at least similar modules. Each module preferably includes a plurality of transceiver channels and a clock source unit. Clock distribution circuitry is provided for distributing the signal of a module's clock source to all of the transceiver channels in that module, and also selectively beyond that module to other modules.
机译:可编程逻辑器件集成电路(“ PLD”)上的收发器电路优选地设置在多个相同或至少相似的模块中。每个模块优选地包括多个收发器通道和时钟源单元。提供了时钟分配电路,用于将模块的时钟源的信号分配到该模块中的所有收发器通道,并且还选择性地将该模块的时钟源的信号分配到其他模块。

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