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Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together
Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together
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机译:可编程逻辑器件收发器体系结构,有助于一起使用各种数量的收发器通道
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摘要
Transceiver circuitry on a programmable logic device integrated circuit (“PLD”) is preferably provided in a plurality of identical or at least similar modules. Each module preferably includes a plurality of transceiver channels and a clock source unit. Clock distribution circuitry is provided for distributing the signal of a module's clock source to all of the transceiver channels in that module, and also selectively beyond that module to other modules.
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