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Instruction retry verification functional equipped information processing equipment and instruction retry verification manner
Instruction retry verification functional equipped information processing equipment and instruction retry verification manner
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机译:指令重试验证功能装备的信息处理设备和指令重试验证方式
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摘要
A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.
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