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dynamically configurable debug interface with concurrent use of debugging of several processor cores
dynamically configurable debug interface with concurrent use of debugging of several processor cores
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机译：可动态配置的调试接口，同时使用多个处理器内核进行调试
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摘要
An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin. IMAGE
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