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Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements
Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements
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机译：支持可重定位位流的设计方法，用于FPGA的动态部分重配置，以减少位流存储需求
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摘要
A method for generating a design for an FPGA provides for partial reconfiguration by allowing relocation of the same single bitstream within different areas of the FPGA, reducing overall design time and PROM storage space needed for the design. The design rules for the method include a requirement that the same frames oriented in the same relative location be available in dynamic areas where a bit stream will be located. Further, the rules require the same relative communication interfaces be available between the dynamic areas and static areas when the bit stream is relocated. Additionally the design rules require global resources, such as clock resources used by the static areas remain the same when the bit stream is relocated.
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