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Apparatus and method for test, characterization, and calibration of microprocessor-based and digital signal processor-based integrated circuit digital delay lines

机译:用于测试,表征和校准基于微处理器和基于数字信号处理器的集成电路数字延迟线的装置和方法

摘要

A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and calibrating the delay line elements. In the test mode, a calibrated pulse is delayed by the delay line while determining the logic state of pulse at two times, the interval between the two times being the same as the pulse width. By adding delay elements, the period of the calibrated pulse as a function of number of delay elements can determine the delay of each delay element. In the calibration mode, the delay line is configured as a ring oscillator and the frequency of the ring oscillator as a function of number of delay elements provides the time delay for the individual elements.
机译:具有处理单元和在其上制造的具有可控制数量的延迟元件的延迟线的电路板包括用于测试和校准延迟线元件的设备。在测试模式下,校准脉冲被延迟线延迟,同时两次确定脉冲的逻辑状态,两次之间的间隔与脉冲宽度相同。通过添加延迟元件,作为延迟元件数量的函数的校准脉冲的周期可以确定每个延迟元件的延迟。在校准模式下,延迟线配置为环形振荡器,并且环形振荡器的频率作为延迟元件数量的函数,为各个元件提供时间延迟。

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