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Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities
Methods of Forming CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities
A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.
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