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LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC

机译：沿漏极扩展介电层的侧壁具有沟道的横向漏极扩展MOSFET

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摘要

An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall. A source region (18) of the first doping type is in the body region (16), a drain region (20) of the first doping type is in the drift region (14), and interconnects (521) are operable to electrically connect the one or more transistors to each other on the integrated circuit (200).

机译：集成电路（ 200 ）在具有半导体表面层的基板（ 10 ）上或之中包括一个或多个晶体管（ 210 ）中的一个，具有顶表面的层。晶体管中的至少一个是漏极扩展金属氧化物半导体（DEMOS）晶体管（ 210 ）。 DEMOS晶体管包括在具有第一掺杂剂类型的表面层中的漂移区（ 14 ），在所述表面层的一部分中或之上的场电介质（ 23 ），在漂移区（ 14 ）内的第二掺杂类型（ 16 ）的体区。主体区域（ 16 ）具有主体壁，该主体壁从表面层的顶表面沿着相邻的场电介质区域的电介质壁的至少一部分向下延伸。栅极电介质（ 21 ）在体壁的至少一部分上。导电栅电极（ 22 ）位于体壁上的栅电介质（ 21 ）上。第一掺杂类型的源极区域（ 18 ）在主体区域（ 16 ）中，第一掺杂类型的漏极区域（ 20 ）掺杂类型位于漂移区（ 14 ）中，并且互连（ 521 ）可用于将一个或多个晶体管彼此电连接到集成电路（ 200 ）。 展开▼

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公开/公告号US2009256212A1

专利类型

公开/公告日2009-10-15

原文格式PDF

申请/专利权人 MARIE DENISON;TAYLOR RICE EFLAND;
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申请/专利号US20080101762

发明设计人 MARIE DENISON;TAYLOR RICE EFLAND;
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申请日2008-04-11

分类号H01L29/00;H01L21/8236;

国家 US

入库时间 2022-08-21 19:36:36

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