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The delay profile generation circuit which features that

机译:延迟分布产生电路的特点是

摘要

PROBLEM TO BE SOLVED: To provide a delay profile generating circuit whose circuit scale is made small and a CDMA receiver that can be downsized by eliminating the need for delay elements in order to solve a problem that a conventional circuit increases the circuit scale because it employs a delay elements. SOLUTION: A correlation arithmetic section (MF) 1 conducts a correlation arithmetic operation between a spread code of a received base band signal and a different spread code, a power arithmetic section (POW) 2 calculates an output level of the section 1, a selector selectively outputs data not delayed or data to be delayed by each symbol number, and an averaging section 8 averages each of the data and data having already averaged relating to data stored in a storage section 9 in the delay profile generating circuit and the CDMA receiver.
机译:解决的问题:提供一种延迟轮廓产生电路,其电路规模较小,并且可以通过消除对延迟元件的需求来减小CDMA接收机的尺寸,以解决传统电路由于采用了这种电路而增加电路规模的问题。延迟元素。解决方案:相关算术部分(MF)1在接收的基带信号的扩展码和不同的扩展码之间进行相关算术运算,功率算术部分(POW)2计算部分1的输出电平,选择器选择性地输出未延迟的数据或将要延迟每个符号号的数据,并且平均部分8对与延迟分布生成电路和CDMA接收机中的存储部分9中存储的数据相关的每个数据和已经平均的数据进行平均。

著录项

  • 公开/公告号JP4315563B2

    专利类型

  • 公开/公告日2009-08-19

    原文格式PDF

  • 申请/专利权人 株式会社日立国際電気;

    申请/专利号JP20000069790

  • 发明设计人 若松 誠;川井 久嗣;

    申请日2000-03-14

  • 分类号H04B1/707;

  • 国家 JP

  • 入库时间 2022-08-21 19:41:46

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